In the design of integrated circuit chips, there is an inherent presence of competing interests grounded in the concept of deriving greater computing power and better performance from a smaller, more dense chip. As the push towards miniaturization of integrated circuit chips increases, designers face some practical limitations to further miniaturization. Such limitations include the number of signal connectors available to satisfy the greater number of transistors and associated circuitry contained on the miniaturized chips, and means to effectively handle heat dissipation generated by the increased number of components on the chip. Furthermore, even when manufacturers increase the surface area of the chip, the result of the circuit miniaturization presents the similar problem of insufficient peripheral surface area to mount the signal connectors. For example, in the construction of very large scale integrated circuits (VLSI circuits), the number of transistors which can be placed on a particular chip, being a function of the surface area of that chip, allows VLSI circuit chips to contain many thousand transistors per square centimeter. Signal connectors have not, to date, been sufficiently reduced in size to accommodate the increased number of transistors.
Current integrated circuit chip designs largely call for power connections to be interspersed among the signal connectors to the integrated circuit chip. For example, in high powered chip designs using a normal 5 volt driving voltage, a chip rated for 50 watts will require approximately 10 amperes of driving current. If one assumes that each signal connection (or lead) can carry about 0.25 amperes, and assuming that 2 leads are required to complete a given electrical path, 80 leads are required just to power the chip. Such connection requirements can severely restrict signal connection to transistor logic located within an integrated circuit chip.
Prior art solutions have only been marginally successful in addressing this connection problem. Such solutions have been directed to the use of one or more leads to supply a ground connection and one or more driving voltage connections. The essence of prior art solutions has been to place at least one layer of metallized material in between other layers of dielectric material to provide a power source to drive the transistor circuitry contained on the surface of the integrated circuit chip. The power source is then made available to transistors and other circuit components by providing holes, or "vias" in the dielectric material.
When the chip circuitry requires voltages of varying levels, prior art solutions have called for a plurality of metallized planes to be placed at various points in the dielectric layers. Another solution has been to provide a single metallized planar power lead with step down resistive networks or operational amplifier (voltage divider) networks located on the surface of the integrated circuit chip.
Although the prior art solutions have somewhat resolved the problem of insufficient signal connections, such solutions have themselves introduced new problems. For example, providing thin metallized planar power supplies sandwiched between dielectric layers resulted in significant resistance for such metallized planes and resultant voltage drops across these planes. These voltage drops could potentially effect logic levels throughout the integrated circuit chip. Also, current density in such thin metallized planes had been high enough to cause what is known as electromigration in the metal. Electromigration is an atomic flux induced in conductors which may be created by a momentum transfer of electrons and tends to reduce the reliability of integrated circuit chips.
It is also known that electromigration of metals is a function of such variables as the density of metallic ions in a conductor, the current density, the diffusion rate, the resistivity of the conductor and the temperature, among other things. Thin metallized planes are known to be more prone to electromigration because of their higher diffusion rates and higher resistivity.
Thermal performance of high-speed, high-power, integrated circuit chips, for example, bipolar integrated circuit chips, has in the past been inadequate to allow for power levels in excess of 100 watts. Traditionally, thermal power dissipated in an integrated circuit chip is conducted through the semiconductor substrate (dielectric) to a heat sink attached to the underside of the chip, away from active circuitry, while the power lead current is delivered to the front active planar circuitry through metallized planes.
State of the art digital integrated circuits can contain more than 100,000 transistors. When filled with high speed logic circuitry, power in excess of 100 watts would be thermally dissipated, if designed for optimum performance. This magnitude of power is very difficult to remove from the relatively small area of an integrated circuit chip. Also, operation at a typical power lead voltage of 5 volts requires the delivery of currents greater than 20 amperes to microscopic structures composed of a dielectric material. This dielectric material, as a result, is exposed to high amperage, significant heat buildups, thermal expansion and resultant thermal stress. Reasonable temperature of the metal/dielectric junction is critical to integrated circuit chip reliability, thereby requiring thermal dissipation techniques to keep pace with increase in power requirements.